1. Field of the Invention
The present invention relates generally to a test mode setting arrangement provided within a microcomputer, and more specifically to such an arrangement which obviates the need for a pin or terminal to be dedicated to testing.
2. Description of the Prior Art
It is a common practice that a manufacturer of microcomputers provides each of the fabricated chips with a test mode setting arrangement or circuit for effectively ascertaining whether a chip has been manufactured correctly or not. Functional testing is usually performed using a LSI (Large Scale Integration) tester which applies a test pattern to a microcomputer input(s) and compares the output(s) therefrom with expected values.
Before turning to the present invention it is deemed preferable to briefly discuss two known test mode setting arrangements with reference to FIGS. 1 and 2.
FIG. 1 is a block diagram showing a microcomputer 10 which includes a known test mode setting arrangement 12, a CPU (Central Processing Unit) 14, an internal memory 16 and a test memory 18. The memories 16, 18 are coupled to the CPU 14 by way of an address bus 17 and an instruction fetch bus 19. For the sake of simplifying the description and drawings, the microcomputer 10 shown in FIG. 1 does not illustrate all of the circuits usually included therein. An external memory 20 is coupled to the CPU 14 through chip pins P4, P5 via address buses 17, 17' and instruction fetch buses 19, 19'.
Before describing the test modes of the FIG. 1 arrangement, two instruction fetch modes will be described.
It is assumed that a test signal 41 applied to a pin P3 assumes a logic 0. If a mode select signal 42 applied to a pin P1 assumes a logic 0, the AND gate 28 issues an instruction fetch mode (IFM) signal IFM 1 assuming a logic 1 while another instruction fetch mode signal IFM 2 from the AND gate 30 assumes a logic 0. In response to the signal IFM 1 assuming a logic 1, the CPU 14 fetches instructions from the external memory 20 and executes same. On the other hand, in the event that the mode select signal 42 assumes a logic 1 (e.g., a power source voltage 5 V), the output of AND gate 28 assumes a logic 0 while the output of the AND gate 30 assumes a logic 1. Thus, the CPU fetches instructions stored in the internal memory 16 and executes same. The instruction fetch modes are not directly concerned with the present invention, and hence further descriptions thereof are deemed redundant.
The test mode implemented by the FIG. 1 arrangement will be described in brief. User programs stored in the internal memories of microcomputers vary from user to user and, accordingly, if all of the user programs are to be verified in terms of operations thereof, it is necessary to obtain individual user's input information and prepare the corresponding different test patterns. However, it is practically impossible to obtain the different user's input data and prepare the corresponding test patterns and then execute microcomputer tests. In order to overcome this problem, the test memory 18, which is dedicated to the test mode, is provided within the microcomputer 10. The manufacturer stores a predetermined set of program instructions in the test memory 18. Following this, the instructions are fetched from the memory 18 and executed by the CPU 14 for diagnostic purposes using a single test pattern. Such a test mode using the test memory 18 will be referred to as TEST MODE 1.
The test mode setting arrangement 12 initiates the above-mentioned TEST MODE 1. In FIG. 1, before bringing this test mode into operation, a reset control signal 44 assuming a logic 0 is applied to the reset signal generator 26 via a pin P2 in order to reset the CPU 14. The reset signal generator 26 issues a reset signal 46 which assumes a power source voltage Vcc (viz., logic 1) in response to the reset control signal 44 assuming logic 0. Thus, the CPU 14 is initialized. In this instance, the test signal 41 continues to assume the power source voltage Vcc (viz., logic 1).
After resetting the CPU 14, when the reset control signal 44 is raised to Vcc, the reset signal 46 assumes a logic 0 by which the CPU is released from the reset condition. Thereafter, when the test signal 41 assumes the power source voltage Vcc (viz., logic 1), the CPU 14 initiates TEST MODE 1 in this particular case.
Recent advances in LSI technology have permitted notable reductions in chip size. However, the full benefit of this size reduction capability has not been realized in that the pins, which are inherently required to be provided along the side(s) of the chips, must have a finite size so as to exhibit the required rigidity and longevity. Thus, it is highly desirable to increase the number of pins available for users. Therefore, the prior art discussed with FIG. 1 has encountered the problem in that it is inherently provided with the pin P3 dedicated to the test mode.
FIG. 2 is a block diagram showing another known test mode setting arrangement 12' which does not require a pin exclusively for test mode use. The arrangement 12' of FIG. 2 differs from the counterpart 12 of FIG. 1 in that: (a) the arrangement 12' is not provided with a pin which is dedicated to the testing of a microcomputer and (b) the arrangement 12' includes a high voltage detector 24. The remaining portions of the FIG. 2 arrangement are identical to those of the FIG. 1 arrangement, and hence further descriptions thereof will be omitted for brevity.
The arrangement 12' of FIG. 2 is provided to initiate TEST MODE 1 in the same manner as the arrangement 12 of FIG. 1. In FIG. 2, before initiating TEST MODE 1, a reset signal 44 assuming a logic 0 is applied to the reset signal generator 26 via the pin P2 in order to reset the CPU 14. The reset signal generator 26 issues a reset signal 46 which assumes a power source voltage Vcc (viz., logic 1) in response to the reset signal 44 assuming logic 0 applied thereto. Thus, the CPU 14 is initialized. In this instance, although the high voltage detector 24 is also supplied with the signal 44 assuming 0, the detector 24 issues a signal 40 assuming a logic 0.
After resetting the CPU 14, when the reset signal 44 is raised to a predetermined high voltage (e.g., a voltage of 12 V or more), the high voltage detector 24 produces the test signal 40' assuming a logic 1 (viz., the power voltage Vcc). In this case, each of fetch mode signals IFM1 and IFM2 assumes a logic 0 irrespective of the value of the mode signal 42. Thus, the CPU initiates the TEST MODE 1 in this particular case.
The test mode setting circuit 12' shown in FIG. 2 is such that, while it does not requires a pin or terminal to be exclusively assigned to the test mode, allowing the number of pins available for users to increase, it requires the provision of the high voltage detector 24. This induces the drawbacks that, normal LSI testers must be modified in order to increase the normal output, which is about 8 V, up to the necessary 12 V level, or alternatively replaced with a much more expensive unit. In either event the second prior art increases the cost of microprocessor fabrication.